1. Field of the Invention
The present invention relates to a method for making a mask in a process of fabricating a semiconductor device, and more particularly, to a method for improving resolution in photolithography in a process of fabricating a semiconductor device.
2. Discussion of the Related Art
Generally, a photolithographic process relates to a process of forming a pattern and is one of the important processes in fabricating a semiconductor device. Recently, with the high integration of semiconductor devices, precision in the photolithographic process is required. This is because the patterns are a small size for highly integrated semiconductor devices and a process that requires a high precision is required for resolution in the small sized pattern. However, the devices for the photolithographic process often fail to keep up with the small sized pattern. In this respect, to enhance resolution of the small sized pattern and pattern fidelity, resolution enhancement technology (RET) has been developed. Examples of the RET include off axis illumination (OAI), sub-resolution assist features (SRAF), and optical proximity correction (OPC). Among them, OPC has been performed in a process as small as 0.18 μm. Examples of OPC include rule based OPC, model based OPC, and hybrid OPC. Hybrid OPC is based on both rule based OPC and model based OPC. Each OPC is selectively performed depending on what design is handled.
Model based OPC is mainly performed in foundries. As shown in FIG. 1, OPC has been conventionally performed for a static random access memory (SRAM) block 100 and a random logic block 102 without classification. OPC will be described in detail with reference to FIGS. 2 and 3. FIG. 2 illustrates bit cells constituting SRAM, and FIG. 3 illustrates an SRAM block 100. The SRAM block 100 shown in FIG. 3 is configured in such a manner that a plurality of bit cells 10 shown in FIG. 2 are repeatedly arranged. Since the OPC has conventionally been performed for the SRAM block 100 and the random logic block 102 without classification, a problem occurs in that performance of the OPC deteriorates due to the SRAM block 100 formed by the repeated patterns of the bit cells. This problem occurs more seriously with high integration.